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HD64F7058BP80L Datasheet(PDF) 8 Page - Renesas Technology Corp |
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HD64F7058BP80L Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 1130 page Rev. 3.0, 09/04, page v of xxxviii Item Page Revisions (See Manual for Details) 10.3.2 DMA Transfer Requests Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits 180, 182 Table amended DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination Bus Mode RS0 RS1 RS2 RS3 RS4 HCAN0 RM0 (HCAN0 receive interrupt) MB0-MB15 Don't care* Burst/cycle- steal 1 1 0 0 0 MB0-MB15: HCAN0 message data 10.3.11 DMAC Access from CPU 193 Description amended The space addressed by the DMAC is 4-cycle space. Therefore, when the CPU becomes the bus master and accesses the DMAC, a minimum of four internal clock cycles ( φ) are required for one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the DMAC is completed in one bus cycle, a longword-size access is automatically divided into two word accesses, requiring two bus cycles (eight basic clock cycles). These two bus cycles are executed consecutively; a different bus cycle is never inserted between the two word accesses. This applies to both write accesses and read accesses. 11.2.21 Offset Base Registers (OSBR) 341 Bit table amended Dedicated input capture registers with the same input trigger signal as that for channel 0 ICR0A Offset Base Registers 1 and 2 (OSBR1, OSBR2) Description amended OSBR1 and OSBR2 are 16-bit read-only registers used exclusively for input capture. Same as the channel 0 input capture register (ICR0A), OSBR1 and OSBR2 use the TI0A input as their trigger signal, and store the TCNT1A or TCNT2A value on detection of an edge. 11.3.1 Overview Channel 10: (3) Multiplied clock correction block 366 Description amended …When the 16-bit correction counter 10F (TCNT10F) value exceeds that in 16-bit correction counter 10E (TCNT10E) , no count-up operation is performed. 11.3.2 Free-Running Counter Operation and Cyclic Counter Operation Figure 11.13 Free-Running Counter Operation and Overflow Timing 367 Figure amended P φ TSTR1 STR0 TCNT0 Clock TCNT0 TSR0 OVF0 00000001 00000002 00000006 00000005 00000004 00000003 |
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