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SH7017F-ZTAT Datasheet(PDF) 7 Page - Renesas Technology Corp |
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SH7017F-ZTAT Datasheet(HTML) 7 Page - Renesas Technology Corp |
7 / 754 page Rev.5.00 Sep. 27, 2007 Page vii of xxxiv REJ09B0398-0500 Main Revisions for This Edition Item Page Revision (See Manual for Details) All — Company name and brand names amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. Description of DTC deleted 1.2 Block Diagram Figure 1.1 Block Diagram of the SH7014 6 Figure amended A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MD3 MD2 MD1 MD0 NMI EXTAL XTAL V CC V CC V CC PLLVCC PLLCAP PLLVSS V CC V CC V SS V SS V SS V SS V SS V SS V SS V SS AV CC AV SS RES WDTOVF : Peripheral address bus : Peripheral data bus : Internal address bus : Internal upper data bus : Internal lower data bus RAM (3 kB)/ cache (1 kB) CPU Direct memory access controller Interrupt controller Bus state controller Serial communi- cation interface ( ×2 channels) Multifunction timer/ pulse unit Compare match timer ( ×2 channels) A/D converter Watch- dog timer V SS V SS V SS Figure 1.2 Block Diagram of the SH7016, SH7017 7 Note amended Note: * V CC in the SH7016, FWP in the SH7017 (except FWE pin in the programmer mode). |
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