HD64F7051 datasheet(8/841 Pages) RENESAS

Part #	HD64F7051

Description	32-Bit RISC Microcomputer SuperH RISC engine Family/

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Manufacturer	RENESAS [Renesas Technology Corp]

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8 / 841 page

Rev. 5.00 Jan 06, 2006 page viii of xx

4.4

Notes on Using..................................................................................................................

58

Section 5 Exception Processing....................................................................................... 61

5.1

Overview...........................................................................................................................

61

5.1.1

Types of Exception Processing and Priority ........................................................

61

5.1.2

Exception Processing Operations.........................................................................

62

5.1.3

Exception Processing Vector Table .....................................................................

63

5.2

Resets ................................................................................................................................

65

5.2.1

Power-On Reset ...................................................................................................

65

5.3

Address Errors ..................................................................................................................

66

5.3.1

Address Error Sources .........................................................................................

66

5.3.2

Address Error Exception Processing....................................................................

67

5.4

Interrupts ...........................................................................................................................

67

5.4.1

Interrupt Sources..................................................................................................

67

5.4.2

Interrupt Priority Level ........................................................................................

68

5.4.3

Interrupt Exception Processing ............................................................................

68

5.5

Exceptions Triggered by Instructions ...............................................................................

69

5.5.1

Types of Exceptions Triggered by Instructions ...................................................

69

5.5.2

Trap Instructions ..................................................................................................

69

5.5.3

Illegal Slot Instructions ........................................................................................

70

5.5.4

General Illegal Instructions..................................................................................

70

5.6

When Exception Sources Are Not Accepted ....................................................................

71

5.6.1

Immediately after a Delayed Branch Instruction .................................................

71

5.6.2

Immediately after an Interrupt-Disabled Instruction............................................

71

5.7

Stack Status after Exception Processing Ends ..................................................................

72

5.8

Notes on Use .....................................................................................................................

73

5.8.1

Value of Stack Pointer (SP) .................................................................................

73

5.8.2

Value of Vector Base Register (VBR) .................................................................

73

5.8.3

Address Errors Caused by Stacking of Address Error Exception Processing ......

73

Section 6 Interrupt Controller (INTC)........................................................................... 75

6.1

Overview...........................................................................................................................

75

6.1.1

Features................................................................................................................

75

6.1.2

Block Diagram .....................................................................................................

76

6.1.3

Pin Configuration.................................................................................................

77

6.1.4

Register Configuration.........................................................................................

77

6.2

Interrupt Sources ...............................................................................................................

78

6.2.1

NMI Interrupts .....................................................................................................

78

6.2.2

User Break Interrupt ............................................................................................

78

6.2.3

IRQ Interrupts ......................................................................................................

78

6.2.4

On-Chip Peripheral Module Interrupts ................................................................

79

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