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H8SX1663 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 1158 page  Rev.1.00 Jun. 07, 2006 Page xi of lii 4.5 Address Error ....................................................................................................................... 84 4.5.1 Address Error Source.............................................................................................. 84 4.5.2 Address Error Exception Handling ......................................................................... 85 4.6 Interrupts .............................................................................................................................. 86 4.6.1 Interrupt Sources..................................................................................................... 86 4.6.2 Interrupt Exception Handling.................................................................................. 87 4.7 Instruction Exception Handling ........................................................................................... 87 4.7.1 Trap Instruction....................................................................................................... 87 4.7.2 Sleep Instruction Exception Handling .................................................................... 88 4.7.3 Exception Handling by Illegal Instruction .............................................................. 89 4.8 Stack Status after Exception Handling................................................................................. 90 4.9 Usage Note........................................................................................................................... 91 Section 5 Interrupt Controller ..............................................................................93 5.1 Features ................................................................................................................................ 93 5.2 Input/Output Pins ................................................................................................................. 95 5.3 Register Descriptions ...........................................................................................................95 5.3.1 Interrupt Control Register (INTCR) ....................................................................... 96 5.3.2 CPU Priority Control Register (CPUPCR) ............................................................. 97 5.3.3 Interrupt Priority Registers A to I, K, L, Q, and R (IPRA to IPRI, IPRK, IPRL, IPRQ, and IPRR)...................................................... 98 5.3.4 IRQ Enable Register (IER) ................................................................................... 100 5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 102 5.3.6 IRQ Status Register (ISR)..................................................................................... 106 5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 107 5.4 Interrupt Sources................................................................................................................ 109 5.4.1 External Interrupts ................................................................................................ 109 5.4.2 Internal Interrupts ................................................................................................. 110 5.5 Interrupt Exception Handling Vector Table....................................................................... 111 5.6 Interrupt Control Modes and Interrupt Operation .............................................................. 116 5.6.1 Interrupt Control Mode 0 ...................................................................................... 116 5.6.2 Interrupt Control Mode 2 ...................................................................................... 118 5.6.3 Interrupt Exception Handling Sequence ............................................................... 120 5.6.4 Interrupt Response Times ..................................................................................... 121 5.6.5 DTC and DMAC Activation by Interrupt ............................................................. 122 5.7 CPU Priority Control Function Over DTC and DMAC..................................................... 125 5.8 Usage Notes ....................................................................................................................... 128 5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 128 5.8.2 Instructions that Disable Interrupts ....................................................................... 129 5.8.3 Times when Interrupts are Disabled ..................................................................... 129 |
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