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H8S2268 Datasheet(PDF) 40 Page - Renesas Technology Corp |
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H8S2268 Datasheet(HTML) 40 Page - Renesas Technology Corp |
40 / 725 page Rev. 4.00 Mar 21, 2006 page xl of lxviii 2.9 Usage Notes ...................................................................................................................... 49 2.9.1 TAS Instruction.................................................................................................... 49 2.9.2 STM/LDM Instruction ......................................................................................... 49 2.9.3 Bit Manipulation Instructions .............................................................................. 49 2.9.4 Access Method for Registers with Write-Only Bits............................................. 51 Section 3 MCU Operating Modes .................................................................................. 55 3.1 Operating Mode Selection................................................................................................. 55 3.2 Register Description.......................................................................................................... 56 3.2.1 Mode Control Register (MDCR) ......................................................................... 56 3.3 Operating Mode ................................................................................................................ 56 3.4 Address Map ..................................................................................................................... 57 Section 4 Exception Handling ......................................................................................... 59 4.1 Exception Handling Types and Priority ............................................................................ 59 4.2 Exception Sources and Exception Vector Table ............................................................... 60 4.3 Reset61 4.3.1 Reset Exception Handling.................................................................................... 61 4.3.2 Interrupts after Reset............................................................................................ 62 4.3.3 State of On-Chip Peripheral Modules after Reset Release................................... 62 4.4 Traces (Supported Only by the H8S/2268 Group)............................................................ 63 4.5 Interrupts ........................................................................................................................... 63 4.6 Trap Instruction................................................................................................................. 64 4.7 Stack Status after Exception Handling.............................................................................. 65 4.8 Usage Note........................................................................................................................ 65 Section 5 Interrupt Controller .......................................................................................... 67 5.1 Features ............................................................................................................................. 67 5.2 Input/Output Pins .............................................................................................................. 70 5.3 Register Descriptions ........................................................................................................71 5.3.1 System Control Register (SYSCR) ...................................................................... 71 5.3.2 Interrupt Priority Registers A to G, I to M, and O (IPRA to IPRG, IPRI to IPRM, IPRO) (H8S/2268 Group Only) ............................................................... 73 5.3.3 IRQ Enable Register (IER) .................................................................................. 74 5.3.4 IRQ Sense Control Registers H and L (ISCRH and ISCRL) ............................... 75 5.3.5 IRQ Status Register (ISR).................................................................................... 77 5.3.6 Wakeup Interrupt Request Register (IWPR)........................................................ 80 5.3.7 Interrupt Enable Register 1 (IENR1) ................................................................... 80 5.4 Interrupt Sources ............................................................................................................... 81 5.4.1 External Interrupts ............................................................................................... 81 5.4.2 Internal Interrupts................................................................................................. 84 |
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