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H83664 Datasheet(PDF) 96 Page - Renesas Technology Corp |
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H83664 Datasheet(HTML) 96 Page - Renesas Technology Corp |
96 / 444 page Section 4 Address Break Rev. 6.00 Mar. 24, 2006 Page 68 of 412 REJ09B0142-0600 4.1 Register Descriptions Address break has the following registers. • Address break control register (ABRKCR) • Address break status register (ABRKSR) • Break address register (BARH, BARL) • Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Bit Bit Name Initial Value R/W Description 7 RTINTE 1 R/W RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. 6 5 CSEL1 CSEL0 0 0 R/W R/W Condition Select 1 and 0 These bits set address break conditions. 00: Instruction execution cycle 01: CPU data read cycle 10: CPU data write cycle 11: CPU data read/write cycle 4 3 2 ACMP2 ACMP1 ACMP0 0 0 0 R/W R/W R/W Address Compare Condition Select 2 to 0 These bits comparison condition between the address set in BAR and the internal address bus. 000: Compares 16-bit addresses 001: Compares upper 12-bit addresses 010: Compares upper 8-bit addresses 011: Compares upper 4-bit addresses 1XX: Reserved (setting prohibited) |
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