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R5F3651EDFC Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R5F3651EDFC Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 829 page A - 4 8.4 CPU Clock and Peripheral Function Clocks.................................................... 119 8.4.1 CPU Clock and BCLK............................................................................... 119 8.4.2 Peripheral Function Clocks (f1, fOCO40M, fOCO-F, fOCO-S, fC32, fC).. 119 8.5 Clock Output Function..................................................................................... 121 8.6 System Clock Protection Function .................................................................. 121 8.7 Oscillation Stop/Re-Oscillation Detect Function .............................................. 122 8.7.1 Operation When CM27 Bit is 0 (Oscillation Stop Detection Reset) .......... 122 8.7.2 Operation When CM27 Bit is 1 (Oscillation Stop, Re-Oscillation Detect Interrupt) ................................................................................................... 123 8.7.3 Using the Oscillation Stop, Re-Oscillation Detect Function ...................... 124 8.8 Notes on Clock Generator............................................................................... 125 8.8.1 Oscillation Circuit Using an Oscillator....................................................... 125 8.8.2 Noise Countermeasure............................................................................. 126 8.8.3 CPU ClockW............................................................................................. 127 8.8.4 Oscillation Stop, Re-Oscillation Detect Function ...................................... 127 8.8.5 PLL Frequency Synthesizer ..................................................................... 128 9. Power Control....................................................................................... 129 9.1 Introduction...................................................................................................... 129 9.2 Registers ......................................................................................................... 129 9.2.1 Flash Memory Control Register 0 (FMR0)................................................ 130 9.2.2 Flash Memory Control Register 2 (FMR2)................................................ 131 9.3 Clock ............................................................................................................... 132 9.3.1 Normal Operating Mode ........................................................................... 132 9.3.2 Mode Transitions ...................................................................................... 136 9.3.3 Wait Mode ................................................................................................ 139 9.3.4 Stop Mode ................................................................................................ 143 9.4 Power Control in Flash Memory ...................................................................... 146 9.4.1 Stopping Flash Memory............................................................................ 146 9.4.2 Reading Flash Memory ............................................................................ 147 9.5 Reducing Power Consumption........................................................................ 149 9.5.1 Ports ......................................................................................................... 149 9.5.2 A/D Converter........................................................................................... 149 9.5.3 D/A Converter........................................................................................... 149 9.5.4 Stopping Peripheral Functions.................................................................. 149 9.5.5 Switching the Oscillation-Driving Capacity ............................................... 149 |
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