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R5F61656C Datasheet(PDF) 10 Page - Renesas Technology Corp |
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R5F61656C Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 892 page  Rev. 2.00 Jun. 28, 2007 Page x of xxiv 2.8.1 Register Direct Rn ............................................................................................... 52 2.8.2 Register Indirect @ERn....................................................................................... 52 2.8.3 Register Indirect with Displacement @(d:2, ERn), @(d:16, ERn), or @(d:32, ERn)....................................................... 52 2.8.4 Index Register Indirect with Displacement @(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 52 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement @ERn+, @−ERn, @+ERn, or @ERn− ................................ 53 2.8.6 Absolute Address @aa:8, @aa:16, @aa:24, or @aa:32....................................... 54 2.8.7 Immediate #xx ..................................................................................................... 56 2.8.8 Program-Counter Relative @(d:8, PC) or @(d:16, PC): ..................................... 56 2.8.9 Program-Counter Relative with Index Register @(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) .................................................. 56 2.8.10 Memory Indirect @@aa:8 ................................................................................... 57 2.8.11 Extended Memory Indirect @@vec:7 ................................................................. 58 2.8.12 Effective Address Calculation ................................................................................ 58 2.8.13 MOVA Instruction.................................................................................................. 60 2.9 Processing States.................................................................................................................. 61 Section 3 MCU Operating Modes ....................................................................... 63 3.1 Operating Mode Selection ................................................................................................... 63 3.2 Register Descriptions ...........................................................................................................64 3.2.1 Mode Control Register (MDCR) ............................................................................ 64 3.2.2 System Control Register (SYSCR) ......................................................................... 66 3.3 Operating Mode Descriptions .............................................................................................. 68 3.3.1 Mode 1.................................................................................................................... 68 3.3.2 Mode 2.................................................................................................................... 68 3.3.3 Mode 4.................................................................................................................... 68 3.3.4 Mode 5.................................................................................................................... 68 3.3.5 Mode 6.................................................................................................................... 69 3.3.6 Mode 7.................................................................................................................... 69 3.3.7 Pin Functions .......................................................................................................... 70 3.4 Address Map ........................................................................................................................ 71 3.4.1 Address Map........................................................................................................... 71 Section 4 Exception Handling ............................................................................. 75 4.1 Exception Handling Types and Priority............................................................................... 75 4.2 Exception Sources and Exception Handling Vector Table .................................................. 76 4.3 Reset .................................................................................................................................... 78 4.3.1 Reset Exception Handling ...................................................................................... 78 |
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