Document Number: 70071

S-71241–Rev. H, 25-Jun-07

www.vishay.com

7

Vishay Siliconix

DG884

TIMING DIAGRAMS

Figure 1. Input Timing Requirements

Presetting Device A

CS for

Device A

CS for

Device B

Address

Address

WR

SALVO

RS

I/O

Select Output 1

Presetting Device B

Donít Care

Donít Care

Select Output 2

Output N

Select Input

Select Input

Input

Reset Occuring at Any Time Results In All Current Event Latches Being Cleared

Input

Figure 2. Output Timing Requirements

PARAMETER DEFINITIONS

Symbol

Parameter

Description

Address to Write

Minimum time address must be valid before WR goes high

Write to Address

Minimum time address must remain valid after WR pulse goes high

WR Pulse

Minimum time of WR pulse width to write address into Next Event latches

Chip Select to WR

Minimum time chip select must be valid before a WR pulse

WR to Chip Select

Minimum time chip select must remain valid after WR pulse

SALVO Pulse

Minimum time of SALVO pulse width

WR to SALVO

Minimum time from WR pulse to SALVOto load new address

SALVO to WR

Minimum time from SALVO pulse to WR to load current address

I/O to Address In

Minimum time I/O must be valid before address applied

RS to SALVO

Minimum time RS must be valid before SALVO pulse

I/O to Output

Minimum time I/O must be valid before address output valid

Address to Output

CS to Output

CS to Address In

Minimum time CS must be valid before address applied if I/O is high

t AO

CS for

Device A

CS for

Device B

Interrogating Device A

Address

Address

WR

SALVO

RS

I/O

Reset Occuring at Any Time Results In All Current Event Latches Being Cleared

Select Current

Event Latch 1

Select Current

Event Latch

Interrogating Device B

Output

O

Latch N

Out N

O

A

Address Output 1

Address Output