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DG428 Datasheet(PDF) 1 Page - Vishay Siliconix |
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DG428 Datasheet(HTML) 1 Page - Vishay Siliconix |
1 / 12 page DG428/429 Vishay Siliconix Document Number: 70063 S-52433—Rev. J, 06-Sep-99 www.vishay.com S FaxBack 408-970-5600 5-1 Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers FEATURES BENEFITS APPLICATIONS D Low rDS(on): 55 W D Low Charge Injection: 1 pC D On-Board TTL Compatible Address Latches D High Speed—tTRANS: 160 ns D Break-Before-Make D Low Power Consumption: 0.3 mW D Improved System Accuracy D Microprocessor Bus Compatible D Easily Interfaced D Reduced Crosstalk D High Throughput D Improved Reliability D Data Acquisition Systems D Automatic Test Equipment D Avionics and Military Systems D Communication Systems D Microprocessor-Controlled Analog Systems D Medical Instrumentation DESCRIPTION The DG428/DG429 analog multiplexers have on-chip address and control latches to simplify design in microprocessor based applications. Break-before-make switching action protects against momentary crosstalk of adjacent input signals. The DG428 selects one of eight single-ended inputs to a common output, while the DG429 selects one of four differential inputs to a common differential output. An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to the power supply rails. An enable (EN) function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. All control inputs, address (Ax) and enable (EN) are TTL compatible over the full specified operating temperature range. The silicon-gate CMOS process enables operation over a wide range of supply voltages. The absolute maximum voltage rating is extended to 44 V. Additionally, single supply operation is also allowed and an epitaxial layer prevents latchup. On-board TTL-compatible address latches simplify the digital interface design and reduce board space in bus-controlled systems such as data acquisition systems, process controls, avionics, and ATE. FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG428 DG428 WR D RS S8 A0 A1 EN A2 V– GND S1 V+ S2 S5 S3 S6 S4 S7 Dual-In-Line Decoders/Drivers 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11 Top View 910 Latches PLCC 14 15 16 17 18 8 7 6 5 4 1 2 319 20 11 10 913 12 Top View EN A2 V– GND S1 V+ S2 S5 S3 S6 Latches Decoders/Drivers |
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