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H8SX1544 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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H8SX1544 Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 974 page Rev.2.00 Oct. 16, 2007 Page ix of liv REJ09B0381-0200 Item Page Revision (See Manual for Details) 9.9.12 Conflict between TCNT Write and Overflow/Underflow Figure 9.54 Conflict between TCNT Write and Overflow 394 Figure 9.54 amended P φ TCNT H'FFFF TCFV flag Address Write TCNT address M TCNT write data T 1 T 2 TGR write cycle Prohibited 12.9.6 Writing to Registers during SCI Transmit or Receive 486 Newly added 13.3.5 I 2C Bus Status Register (ICSR) 502 Description added Bit Bit Name Initial Value R/W Description 7 TDRE 0 R/W Transmit Data Register Empty [Setting condition] • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty • When TRS is set to 1 • When the start condition has been issued • In slave mode, after changing from receive mode to transmit mode 13.4.1 I 2C Bus Format Figure 13.3 I 2C Bus Formats 507 Figure 13.3 amended (a) I 2C Bus Format m: Transfer frame count (m ≥1) I 2C Bus Format (start condition retransmission) m1 and m2: 1: Transfer frame count (m1 and m2 ≥1) 13.4.4 Slave Transmit Operation 512 Description amended 1. … ICCRA to 1. Set the WAIT in ICMR and CKS3 to CKS0 in ICCRA, and perform other initial settings. … 13.4.5 Slave Receive Operation 515 Description amended 1. … ICCRA to 1. Set the WAIT in ICMR and CKS3 to CKS0 in ICCRA, and perform other initial settings. … 13.5 Interrupt Request Table 13.3 Interrupt Requests 521 Table 13.3 amended Abbreviation of NACK detection and arbitration lost amended (Before) MAKI → (After) NAKI |
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