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H8S2630 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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H8S2630 Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 1547 page Rev. 6.00 Feb 22, 2005 page x of lx Item Page Revision (See Manual for Details) 3.3.1 Mode 4 85 Description amended Ports 1, A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. 3.3.2 Mode 5 85 Description amended Ports 1, A, B, and C function as an address bus, port D function as a data bus, and part of port F carries bus control signals. 3.3.3 Mode 6 85 Description amended Ports 1, A, B, and C function as input port pins immediately after a reset. Address output can be performed by setting the corresponding DDR (data direction register) bits to 1. 3.5 Address Map in Each Operating Mode Figure 3-4 Memory Map in Each Operating Mode in the H8S/2635 91 Figure 3-4 added Figure 3-5 Memory Map in Each Operating Mode in the H8S/2634 92 Figure 3-5 added 4.1.1 Exception Handling Types and Priority 93 Note * amended Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... Table 4-1 Exception Types and Priority 93 Note 4 amended Note: 4. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask and W-mask versions, and H8S/2635 Group only. ... 4.1.3 Exception Vector Table Table 4-2 Exception Vector Table 95 Note 3 amended Note: 3. ... Subclock functions are available in the U-mask and W-mask versions, and H8S/2635 Group only. 4.4 Interrupts 100 Note added Note: The DTC, PBC, and IIC are not implemented in the H8S/2635 Group. Figure 4-4 Interrupts Sources and Number of Interrupts 100 Note *3 added HCAN (4)* 3 Note: 3. 2 Sources in the H8S/2635 Group. |
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