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SH7606 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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SH7606 Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 532 page Rev. 4.00 Sep. 13, 2007 Page xi of xxvi 7.5.4 Extension of Chip Select ( CSn) Assertion Period................................................. 153 7.5.5 SDRAM Interface ................................................................................................. 155 7.5.6 Byte-Selection SRAM Interface ........................................................................... 180 7.5.7 PCMCIA Interface ................................................................................................ 184 7.5.8 Wait between Access Cycles ................................................................................ 190 7.5.9 Others.................................................................................................................... 190 Section 8 Clock Pulse Generator (CPG)............................................................193 8.1 Features.............................................................................................................................. 193 8.2 Input/Output Pins ...............................................................................................................196 8.3 Clock Operating Modes ..................................................................................................... 196 8.4 Register Descriptions ......................................................................................................... 198 8.4.1 Frequency Control Register (FRQCR) ................................................................. 198 8.5 Changing Frequency .......................................................................................................... 200 8.5.1 Changing Multiplication Ratio ............................................................................. 200 8.5.2 Changing Division Ratio....................................................................................... 201 8.5.3 Changing Clock Operating Mode ......................................................................... 202 8.6 Notes on Board Design ...................................................................................................... 203 Section 9 Watchdog Timer (WDT)....................................................................205 9.1 Features.............................................................................................................................. 205 9.2 Register Descriptions ......................................................................................................... 206 9.2.1 Watchdog Timer Counter (WTCNT).................................................................... 206 9.2.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 207 9.2.3 Notes on Register Access...................................................................................... 209 9.3 WDT Operation ................................................................................................................. 210 9.3.1 Canceling Software Standbys ............................................................................... 210 9.3.2 Changing Frequency ............................................................................................. 211 9.3.3 Using Watchdog Timer Mode .............................................................................. 211 9.3.4 Using Interval Timer Mode .................................................................................. 212 9.4 Usage Note......................................................................................................................... 212 Section 10 Power-Down Modes ........................................................................213 10.1 Features.............................................................................................................................. 213 10.1.1 Types of Power-Down Modes .............................................................................. 213 10.2 Input/Output Pins ...............................................................................................................215 10.3 Register Descriptions ......................................................................................................... 215 10.3.1 Standby Control Register (STBCR)...................................................................... 216 10.3.2 Standby Control Register 2 (STBCR2)................................................................. 217 10.3.3 Standby Control Register 3 (STBCR3)................................................................. 218 |
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