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H8S2612 Datasheet(PDF) 8 Page - Renesas Technology Corp |
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H8S2612 Datasheet(HTML) 8 Page - Renesas Technology Corp |
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8 / 609 page  Rev. 6.00 Mar 15, 2006 page viii of xxxvi Item Page Revision (See Manual for Details) 11.8.3 Register Descriptions 277, 278 Bit 7 to 0 description of Input level control/status register amended (Before) P φ/8 clock → (After) φ/8 clock (Before) P φ/16 clock → (After) φ/16 clock (Before) P φ/128 clock → (After) φ/128 clock 14.3.9 Bit Rate Register (BRR) Table 14.2 Relationships between the N Setting in BRR and Bit Rate B 331 Table 14.2 amended Mode Bit Rate Error Asynchronous Mode B = 64 × 2 2n-1 × (N + 1) φ × 106 Error (%) = { B × 64 × 2 2n-1 × (N + 1) − 1 } × 100 φ × 106 Clocked Synchronous Mode B = 8 × 2 2n-1 × (N + 1) φ × 106 — Smart Card Interface Mode B = S × 2 2n+1 × (N + 1) φ × 106 Error (%) = { B × S × 2 2n+1 × (N + 1) − 1 } × 100 φ × 106 14.9.7 Notes when Switching from SCK Pin to Port Pin 382 Problem in Operation Description amended (Before) C/A → (After) C/A 15.3.20 HCAN Monitor Register (HCANMON) 414 Table amended Bit Bit Name Initial Value R/W Description 7 to 2 — Undefined — Reserved Only 0 should be written to these bits. 18.2 Module Transitions Figure 18.2 Flash Memory State Transitions 457 Figure 18.2 amended (Before) RES = 0 → (After) RES = 0 18.9.3 Error Protection 479 Description amended ... However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. ... |
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