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H836087 Datasheet(PDF) 97 Page - Renesas Technology Corp |
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H836087 Datasheet(HTML) 97 Page - Renesas Technology Corp |
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97 / 506 page  Section 5 Clock Pulse Generators CPG0200A_000020020200 Rev. 2.00 Sep. 23, 2005 Page 67 of 472 REJ09B0160-0200 Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. Figure 5.1 shows a block diagram of the clock pulse generators. System clock oscillator Subclock oscillator Subclock divider Duty correction circuit System clock divider Prescaler S (13 bits) Prescaler W (5 bits) OSC1 OSC2 X1 X2 System clock pulse generator φOSC (fOSC) φOSC (fOSC) φW (fW) φW/2 φW/4 φSUB φ/2 to φ/8192 φW/8 φ φOSC/8 φOSC φOSC/16 φOSC/32 φOSC/64 φW/8 to φW/128 Subclock pulse generator Figure 5.1 Block Diagram of Clock Pulse Generators The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φ SUB. The system clock is divided by prescaler S to become a clock signal from φ/8192 to φ/2, and the subclock is divided by prescaler W to become a clock signal from φw/128 to φw/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules. |
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