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H836087 Datasheet(PDF) 95 Page - Renesas Technology Corp |
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H836087 Datasheet(HTML) 95 Page - Renesas Technology Corp |
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95 / 506 page  Section 4 Address Break Rev. 2.00 Sep. 23, 2005 Page 65 of 472 REJ09B0160-0200 4.2 Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU. Figures 4.2 show the operation examples of the address break interrupt setting. NOP instruc- tion prefetch Register setting • ABRKCR = H'80 • BAR = H'025A Program 0258 025A 025C 0260 0262 : * NOP NOP MOV.W @H'025A,R0 NOP NOP : 0258 Address bus φ Interrupt request 025A 025C 025E SP-2 SP-4 NOP instruc- tion prefetch MOV instruc- tion 1 prefetch MOV instruc- tion 2 prefetch Internal processing Stack save Interrupt acceptance Underline indicates the address to be stacked. When the address break is specified in instruction execution cycle Figure 4.2 Address Break Interrupt Operation Example (1) |
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