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H838776 Datasheet(PDF) 79 Page - Renesas Technology Corp |
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H838776 Datasheet(HTML) 79 Page - Renesas Technology Corp |
79 / 594 page Section 3 Exception Handling Rev. 1.00 Dec. 18, 2006 Page 57 of 568 REJ09B0348-0100 3.2 Reset A reset has the highest exception priority. Table 3.2 shows the three sources that cause a reset. Table 3.2 Interrupt Sources that Cause a Reset Origin of Interrupt Source Description RES pin Low-level input Power-on reset circuit Rising of the power-supply voltage (Vcc) For details, see section 20, Power-On Reset Circuit. Watchdog timer Counter overflow For details, see section 14, Watchdog Timer. 3.2.1 Reset Exception Handling When a reset is generated, all processing halts and this LSI enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. To ensure that this LSI be reset, the RES pin has to be held low for the oscillation stabilization time of the system clock oscillator either after power-on or when the system clock oscillator is halted. If the system clock oscillator is functioning, the RES pin has to be held low for the number of the t REL state as is specified by the electrical characteristics. When a reset source has been raised, this LSI starts reset exception handling as follows. 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit in CCR is set to 1. 2. The reset exception handling vector address (H'0000 and H'0001) is read and transferred to the PC, and then program execution starts from the address indicated by the PC. The sequence of the reset exception handling caused by the reset pin is shown in figure 3.1. |
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