Renesas LSIs

M5M5T5672TG – 20

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

11/24

Preliminary

M5M5T5672TG-20 REV.1.0

(3)READ TIMING

Note28.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.

Note29. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.

Read A2

A1

A2

A3

Q(A1)

Q(A2)

Q(A2+1)

Q(A2+2)

Q(A2+3)

Q(A2)

Q(A3)

Q(A3+1)

CLK

CKE#

E#

ADV

W#

BWx#

ADD

DQ

G#

Read A1

Burst Read

A2+1

Stall

Burst Read

A2+2

Burst Read

A2+3

Burst Read

A2

Deselect

Continue

Deselect

Read A3

Burst Read

A3+1

Burst Read

A3+2

Burst Read

A3+3

DON'T CARE

UNDEFINED