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HA16114PJ Datasheet(PDF) 3 Page - Renesas Technology Corp |
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HA16114PJ Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 38 page HA16114P/PJ/FP/FPJ, HA16120FP/FPJ Rev.2.0, Sep.18.2003, page 3 of 37 Pin Arrangement (Top view) 116 Note: 1. Pin 1 (GND) and Pin 8 (P.GND) must be connected each other with external wire. 215 314 413 512 611 710 8 Vref ADJ DB ON/ OFF TM CL( −) VIN OUT 9 GND*1 SYNC RT CT IN( −) E/O IN(+) P.GND*1 Pin Description Pin No. Symbol Function 1 GND Signal ground 2 SYNC External sync signal input (synchronized with falling edge) 3R T Oscillator timing resistor connection (bias current control) 4C T Oscillator timing capacitor connection (sawtooth voltage output) 5 IN(–) Inverting input to error amplifier 6 E/O Error amplifier output 7 IN(+) Non-inverting input to error amplifier 8 P.GND Power ground 9 OUT Output (pulse output to gate of power MOS FET) 10 V IN Power supply input 11 CL(–) Inverting input to current limiter 12 TM Timer setting for intermittent shutdown when overcurrent is detected (sinks timer transistor current) 13 ON/ OFF IC on/off control (off below approximately 0.7 V) 14 DB Dead-band duty cycle control input 15 ADJ Reference voltage (Vref) adjustment input 16 Vref 2.5 V reference voltage output |
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