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STV9410P Datasheet(PDF) 5 Page - STMicroelectronics |
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STV9410P Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 25 page  TIMINGS (VDD =5V ±5%, VSS =0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz, VIL = 0.8V, VIH =2V, VOL = 0.4V, VOH = 2.4V, CL = 50pF, unless otherwise specified) Symbol Parameter Min Typ Max Unit SERIAL INTERFACE NCS, SCK, SDA (Figure 1) Tcsl NCS low to SCK falling edge 0 ns Tsch SCK pulse width high 80 ns Tscl SCK pulse width low 80 ns fSCK Serial Clock Frequency 4 MHz Tsds Set up time of SDA on SCK rising edge 20 ns Tsdh Hold time of SDA after SCK rising edge 20 ns Tsdv Access time in read mode 50 ns Tsdx Hold data in read mode 0 ns Tsdz Serial interface disable time 50 ns Tread Delay before Valid Data 2 µs OSCILLATOR INPUT (XTI) (Figure 1) Twh Clock high level 30 ns Twl Clock low level 30 ns Fclk Clock frequency 8 10 MHz RESET (VREF) Tres Reset Low level pulse 2 µs OUTPUT SIGNALS SDA, CSYNC,VSYNC, R, G, B, I, SYNC IN, DF, XTO, CKO, POR (Figure 2) Tph,Tpl Propagation time CL =30 pF CL = 100 pF 50 100 ns ns Tskew Skew between R, G, B, I signals 30 ns (VDD =5V ±5%, VSS =0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz, VOL = 0.2VDD,VOH = 0.8VDD,CL = 100pF, unless otherwise specified) LCD INTERFACE D0, D1, D2, D3, CKD, LOAD, DF, FRAME (Figure 3) tCYC CKD Shift Clock Period 4 x Pxtal ns tCH CKD Clock High 150 ns tCL CKD Clock Low 150 ns tWLD Load Pulse Width 150 ns tSU Data Set-up Time 150 ns tDH Data Hold Time 150 ns tDF DF Delay from Load 100 ns tSUF Frame Set-up before Load 150 ns STV9410 5/25 |
Similar Part No. - STV9410P |
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Similar Description - STV9410P |
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