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HD74HC294FPEL Datasheet(PDF) 1 Page - Renesas Technology Corp |
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HD74HC294FPEL Datasheet(HTML) 1 Page - Renesas Technology Corp |
1 / 10 page Rev.2.00 Jan 31, 2006 page 1 of 9 HD74HC292/HD74HC294 Programmable Frequency Divider/Digital Timer REJ03D0608–0200 (Previous ADE-205-486) Rev.2.00 Jan 31, 2006 Description This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which initializes the internal flip-flop states. Test Point outputs (TP1, TP2, TP3) are provided with HD74HC292 to facilitate incoming inspections. Test Point output is provided with HD74HC294 to facilitate incoming inspections. Features • High Speed Operation: t pd (Clock to Q) = 16 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: V CC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: I CC (static) = 4 µA max (Ta = 25°C) • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC292P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74HC294FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table CLR CLK1 CLK2 Q Output Mode L X X Cleared to L H L Count H L Count H H X Inhibit H X H Inhibit H : high level L : low level |
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