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HD74HC166FPEL Datasheet(PDF) 1 Page - Renesas Technology Corp |
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HD74HC166FPEL Datasheet(HTML) 1 Page - Renesas Technology Corp |
1 / 7 page Rev.3.00, Jan 31, 2006 page 1 of 6 HD74HC166 Parallel-load 8-bit Shift Register REJ03D0582-0300 Rev.3.00 Jan 31, 2006 Description This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Features • High Speed Operation: t pd (Clock to QH) = 14 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: V CC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: I CC (static) = 4 µA max (Ta = 25°C) • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC166P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74HC166FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Parallel Internal outputs Output Clear Shift/Load Clock Inhibit Clock Serial A ··· H QA QB QH L X X X X X L L L H X L L X X QA0 QB0 QH0 H L L X a ··· h a b h H H L H X H QAn QGn H H L L X L QAn QGn H X H X X QA0 QB0 QH0 QAo to QHo = Outputs remain unchanged. QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input. H : High level L : Low level X : Irrelevant |
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