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7548_0710 Datasheet(PDF) 78 Page - Renesas Technology Corp |
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7548_0710 Datasheet(HTML) 78 Page - Renesas Technology Corp |
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78 / 84 page  Rev.2.01 Oct 15, 2007 Page 78 of 81 REJ03B0210-0201 7548 Group 6. Reading from and Writing to Timer A If the timer A count source clock and φSOURCE are different clocks, timer A cannot be read or written during its counting. Select the same clock or set timer A to stop counting to enable read and write operations. •Timer A cannot be read/written in the following conditions: Timer A count source: XCIN input clock φSOURCE: Clock other than XCIN input clock or Timer A count source: Low-speed on-chip oscillator output φSOURCE: Clock other than low-speed on-chip oscillator 7. Count Source of Timer A The XCIN input clock can be selected as the count source of timer A only if the 32 kHz quartz crystal oscillator is selected by the oscillation method selection bit in FSROM1. Notes on Output Compare (1) If timer A is stopped, when a value is written to the capture/compare register it is immediately transferred to the compare latch. In addition, if timer A is stopped and the compare x trigger enable bit is set to “1”, the output latch is initialized. (2) Do not write the same data to both of compare latch x0 and x1. (3) When setting value of the compare latch is larger than timer setting value, compare match signal is not generated. Accordingly, the output waveform is fixed to “L” or “H” level. However, when setting value of another compare latch is smaller than timer setting value, this compare match signal is generated. Accordingly, compare interrupt occurs. (4) When the compare x trigger enable bit is cleared to “0” (disabled), the match trigger to the waveform output circuit is disabled, and the output waveform can be fixed to “L” or “H” level. However, in this case, the compare match signal is generated. Accordingly, compare interrupt occurs. Notes on Input Capture (1) When the low-speed on-chip oscillator output or XCIN input clock is selected as the count source of timer A, input capture can be used only if the same clock source is selected as φSOURCE and as the count source of timer A. (2) When writing “1” to capture y software trigger bit of capture latch 00 and 01 at the same time, or external trigger and software trigger occur simultaneously, if capture latches 00 and 01 are input simultaneously, the set value of capture 0 status bit is undefined. (3) When setting the interrupt active edge selection bit and noise filter clock selection bit of capture 0 the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. 1Set the capture interrupt enable bit to “0” (disabled). 2Set the interrupt edge selection bit or noise filter clock selection bit. 3Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. 4Set the capture interrupt enable bit to “1” (enabled). (4) When the capture interrupt is used as the interrupt for return from stop mode, set the capture 0 noise filter clock selection bits to “00 (Filter stop)”. |
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