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M37512F8HP Datasheet(PDF) 46 Page - Renesas Technology Corp |
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M37512F8HP Datasheet(HTML) 46 Page - Renesas Technology Corp |
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46 / 87 page  Feb 18, 2005 page 46 of 85 REJ03B0122-0101 7512 Group OVER CURRENT DETECTOR Over current detector detects the over current which flows through the sense resistor connected between ISENS1 pin and ISENS0 pin, and turn off the discharge control FET to stop battery from dis- charging or charging. In the low power state, and when current integrator disables, wake up current detector which detects ap- proximate 1mA current and generates the interrupt is also built-in. Discharge Short Current Detector Discharge short current detector detects the discharge short current(10A-47.5A) with 10m Ω sense resistor. Setting discharge short current detect enable bit of the discharge short current de- tect control register(000F16) “1”, discharge short current detector starts the operation. The compare voltage is determined by setting the discharge short current detect voltage select bit of the dis- charge short current detect control register, and the detect time is determined by setting the discharge short current detect time set up bit of the current detect time set up register 1(001116). The potential difference between sense resistor exceeds the com- pare voltage and continue more than detect time, then discharge short current detect flag(bit 2 of 001316) becomes “1”, and dis- charge short current detect interrupt occurs. Enabling interrupt for discharge short current detect is determined by discharge short current interrupt enable bit(bit 4 of 000F16). And in case of the FET control enable bit is “1”, The FET control signal is generated from DFETCNT pin with discharge short cur- rent interrupt. The polarity of the FET control signal is determined by setting the discharge FET control polarity switch bit(bit 5 of 000F16). Setting the discharge short current detect restart bit(bit 6 of 001316) “1” makes the discharge short current detect state clear. Discharge Over Current Detector Discharge over current detector detects the discharge over current(5A-20.5A) with 10m Ω sense resistor. Setting discharge over current detect enable bit of the discharge over current detect control register(001016) “1”, discharge over current detector starts the operation. The compare voltage is determined by setting the discharge over current detect voltage select bit of the discharge over current detect control register(001016), and the detect time is determined by setting the discharge over current detect time set up bit of the current detect time set up register 1(001116). The potential difference between sense resistor exceeds the com- pare voltage and continue more than detect time, then discharge over current detect flag(bit 1 of 001316) becomes “1”, and dis- charge over current detect interrupt occurs. Enabling interrupt for discharge over current detect is determined by discharge over current interrupt enable bit. And in case of the discharge FET control enable bit is “1”, the FET control signal is generated from DFETCNT pin with discharge over current inter- rupt. Setting the discharge overt current detect restart bit(bit5 of 001316) “1” makes the discharge over current detect state clear. Wake Up Current Detector Wake up current detector detects approximate 1A current with 10m Ω sense resistor. Setting wake up current detect enable bit of the wake up current detect control register 1(001216) “1”, wake up current detector starts the operation. The sensing voltage is 10 times amplified and compared by the comparator. The comparator is comparing every 3.9msec, and more than 1A current is keeping for about 62msec, wake up current detect flag(bit 0 of 001316) be- comes “1”, and the wake up current detect interrupt occurs. The enabling interrupt for wake up current detect is determined by wake up current detect interrupt enable bit(bit6 of 001216). Setting the wake up current detect restart bit “1” makes the wake up cur- rent detect state clear. The offset calibration of the amplifier and comparator is able to be adjusted by setting the wake up current compare voltage select bit. Setting the wake up current detect calibration enable bit(bit5 of 001416) “1”, calibration mode starts. In the calibration mode, input of level shift circuit is connected to internal GND, and it is possible to measure the comparator threshold voltage at 0V input state, with setting wake up current detect compare voltage select bit. Then set the wake up current detect compare voltage select bit the value which is added comparator threshold voltage at 0V state and 0.1V(1A worth voltage). Charge Over Current Detector Charge over current detector detects the charge over current (10A-25A) with 10m Ω sense resister. Setting charge over current detect enable bit of the charge over current detect control register (0FF016) "1", charge over current detector starts the operation. The compare voltage is determined by setting the charge over current detect voltage select bit of the charge over current detect control register (0FF016), and the detect time is determined by set- ting the charge over current detect time set up bit of the current detect time set up register 2 (0FF116). The potential difference between sense resister exceeds the com- pare voltage and continue more than detect time, then charge over current detect flag (bit 3 of 001316) becomes "1", and charge over current detect interrupt occurs. Enabling interrupt for charge over current detect is determined by charge over current interrupt enable bit. And in case of the charge FET control enable bit is "1", the charge FET control signal is gen- erated from CFETCNT pin with charge over current interrupt. The polarity of the FET control signal is determined by setting the charge FET control polarity switch bit (bit 5 of 0FF016). Setting the charge over current detect restart bit (bit 7 of 001316) "1" makes the charge over current detect state clear. SFR Protect Control Register SFR protect control register(002916), bit of MISRG2 (003716) and bit4,5 of MISRG (003816) protect SFR from changing the contents easily cause of like microcomputer runs away. When the bit of SFR protect control register bit of MISRG2, bit 4,5 of MISRG is “0”, corresponded bit register is protected. Writing to the protected register, write “1” to the corresponded bit of protect register, then write the protected register in succession. If other register is written, the contents of SFR protect register is cleared “00”. |
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