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M37151MF-XXXFP Datasheet(PDF) 52 Page - Renesas Technology Corp |
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M37151MF-XXXFP Datasheet(HTML) 52 Page - Renesas Technology Corp |
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52 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 52 of 136 REJ03B0129-0100Z 8.10.2 Clamping Circuit and Low-pass Filter The clamp circuit clamps the sync chip part of the composite video signal input from the CVIN pin. The low-pass filter attenuates the noise of the clamped composite video signal. The CVIN pin to which com- posite video signal is input requires an external capacitor (0.1 µF) coupling. Pull down the CVIN pin with a resistor of hundreds of kilo- ohms to 1 M Ω. In addition, we recommend installing a simple low- pass filter externally, using a resistor and a capacitor at the CVIN pin (refer to Figure 8.10.1). 8.10.3 Sync Slice Circuit This circuit takes out a composite sync signal from the output signal of the low-pass filter. 8.10.4 Synchronous Signal Separation Circuit This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit. (1) Horizontal Synchronous Signal (Hsep) A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync signal. (2) Vertical Synchronous Signal (Vsep) As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit 4 of data slicer control regis- ter 2 (address 00E116). •Method 1 The LOW level width of the composite sync signal is measured. If this width exceeds a certain time, a Vsep signal is generated in synchronization with the rising of the timing signal immediately after this LOW level. •Method 2 The LOW level width of the composite sync signal is measured. If this width exceeds a certain time, it is detected whether a falling of the composite sync sig- nal exits or not in the LOW level period of the timing signal immediately after this LOW level. If a falling exists, a Vsep signal is generated in synchronization with the rising of the timing signal (refer to Figure 8.10.6). Figure 8.10.6 shows a Vsep generating timing. The timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the composite sync signal. As shown in Figure 8.10.7, when the A level matches the B level, this bit is “0.” In the case of a mismatch, the bit is “1.” Fig. 8.10.6 Vsep Generating Timing (method 2) Composite s Timing signal Vsep signal Measure LOW period A Vsep signal is generated at a rising of the timing signal immediately after the LOW level width of the composite sync signal exceeds a certain time. |
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