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M37151MA Datasheet(PDF) 54 Page - Renesas Technology Corp |
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M37151MA Datasheet(HTML) 54 Page - Renesas Technology Corp |
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54 / 138 page  M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP Rev.1.00 Nov 01, 2002 page 54 of 136 REJ03B0129-0100Z 8.10.6 Data Slice Line Specification Circuit (1) Specification of data slice line This circuit determines the lines on to which caption data is super- imposed. Data can be sliced for line 21 and one arbitrary line in both field (2 lines total per field). The caption position register (ad- dress 00E616) is used for each setting (refer to Table 8.10.1). The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the counter value matches the value specified by bits 4 to 0 of the caption position register, this Hsep is sliced. The values of “0016” to “1F16” can be set in the caption position register (when setting only one arbitrary line). Figure 8.10.8 shows the signals in the vertical blanking interval. Figure 8.10.9 shows the structure of the caption position register. (2) Specification of line to set slice voltage Table 8.10.1 shows which field and line generates the reference slice voltage for the clock run-in pulse of each line. The field to generate slice voltage is specified by bit 1 of data slicer control register 1. The line to generate slice voltage for one field is speci- fied by bits 6 and 7 of the caption position register (refer to Table 8.10.1). Fig. 8.10.8 Signals in Vertical Blanking Interval (3) Field determination The field determination flag can be read out by bit 3 of data slicer control register 2. This flag changes at the falling edge of Vsep. Video signal Vertical blanking interval Composite video signal Count value to be set in the caption position register (“0F 16” in this case) Hsep Vsep Hsep Magnified drawing Clock run-in Start bit + 16-bit data Start bit Window for deteminating clock-run-in Composite video signal Line 21 1 appropriate line is set by the caption position register (when setting line 19) |
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