M38B71M1 datasheet(56/110 Pages) RENESAS | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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38B7 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

Fig. 55 Timing using digit interrupt

FLD Automatic Display Start

Automatic display starts by setting both the automatic display con-

trol bit (bit 0 of address 0EF416) and the display start bit (bit 1 of

address 0EF416) to “1”. The RAM contents at a location apart from

the start address of the automatic display RAM for each port by

(FLD data pointer (address 0EF816) – 1) are output to each port.

The FLD data pointer (address 0EF816) counts down in the Tdisp

interval. When the count results in “FF16”, the pointer is reloaded

and starts counting over again. Before setting the display start bit

(bit 1 of address 0EF416) to “1”, be sure to set the FLD/port switch

registers, digit output set switch registers, FLDC mode register,

Tdisp time set register, Toff1 time set register, Toff2 time set regis-

ter, and FLD data pointer.

During FLD automatic display, the display start bit always keeps

“1”, and FLD automatic display can be interrupted by writing “0” to

this bit.

Key-scan and Interrupt

Either the FLD digit interrupt or FLD blanking interrupt can be se-

lected using the Tscan control bits (bits 2, 3 of address 0EF416).

The FLD digit interrupt is generated when the Toff1 time in each

timing expires (at rising edge of digit output). Key scanning that

makes use of FLD digits can be achieved using each FLD digit in-

terrupt. To use FLD digit interrupts for key scanning, follow the

procedure described below:

(1) Read the port value each time the interrupt occurs.

(2) The key is fixed on the last digit interrupt.

The output digit positions can be determined by reading the FLD

data pointer (address 0EF816).

FLD digit output

Tdisp

Tn-1 Tn-2

Toff1

FLD digit interrupt generated at the rising edge of digit (each timing)

Repeat cycle

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