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M38B71M1 Datasheet(PDF) 41 Page - Renesas Technology Corp |
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M38B71M1 Datasheet(HTML) 41 Page - Renesas Technology Corp |
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41 / 110 page 
38B7 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 40 Fig. 40 Structure of serial I/O2 related register b7 b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) Serial I/O2 status register (SIO2STS : address 001E16) Serial I/O2 control register (SIO2CON : address 001D16) b0 b0 b7 UART control register (UARTCON : address 003816) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P65/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) BRG clock switch bit 0: XIN or XCIN (depends on internal system clock) 1: XCIN Serial I/O2 clock I/O pin selection bit 0: SCLK21 (P67/SCLK22 pin is used as I/O port or SRDY2 output pin.) 1: SCLK22 (P66/SCLK21 pin is used as I/O port.) Not used (return “1” when read) b0 BRG count source selection bit (CSS) 0: f(XIN) or f(XCIN)/2 or f(XCIN) 1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4 Serial I/O2 synchronous clock selection bit (SCS) 0: BRG/ 4 (when clock synchronous serial I/O is selected) BRG/16 (UART is selected) 1: External clock input (when clock synchronous serial I/O is selected) External clock input/16 (UART is selected) SRDY2 output enable bit (SRDY) 0: P67 pin operates as ordinary I/O pin 1: P67 pin operates as SRDY2 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O2 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O2 enable bit (SIOE) 0: Serial I/O2 disabled (pins P64 to P67 operate as ordinary I/O pins) 1: Serial I/O2 enabled (pins P64 to P67 operate as serial I/O pins) |
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