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M38B71M1 Datasheet(PDF) 34 Page - Renesas Technology Corp

Part No. M38B71M1
Description  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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M38B71M1 Datasheet(HTML) 34 Page - Renesas Technology Corp

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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
33
Fig. 27 SBUSY1 input operation (internal synchronous clock)
Fig. 28 SBUSY1 input operation (external synchronous clock)
(4) Handshake signal
1. SSTB1 output signal
The SSTB1 output is a signal to inform an end of transmission/re-
ception to the serial transfer destination . The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O ini-
tialization bit (b4) is reset to “0”, the SSTB1 output goes to “L”, or
the SSTB1 output goes to “H”.
At the end of transmit/receive operation, when the data of the se-
rial I/O1 register is all output from SOUT1, pulses are output in the
period of 1 cycle of the transfer clock so as to cause the SSTB1
output to go “H” or the SSTB1 output to go “L”. After that, each
pulse is returned to the initial status in which SSTB1 output goes to
“L” or the SSTB1 output goes to “H”.
Furthermore, after 1 cycle, the serial transfer status flag (b5) is re-
set to “0”.
In the automatic transfer serial I/O mode, whether the SSTB1 out-
put is to be active at an end of each 1-byte data or after
completion of transfer of all data can be selected by the SBUSY1
output • SSTB1 output function selection bit (b4 of address 001A16)
of serial I/O1 control register 2.
2. SBUSY1 input signal
The SBUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H”
level signal into the SBUSY1 input and an “L” level signal into the
SBUSY1 input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level sig-
nal into the SBUSY1 input and an “H” level signal into the SBUSY1
input in the period of 1.5 cycles or more of the transfer clock.
Then, transfer clocks are output from the SCLK1 output.
When an “H” level signal is input into the SBUSY1 input and an “L”
level signal into the SBUSY1 input after a transmit/receive opera-
tion is started, this transmit/receive operation are not stopped
immediately and the transfer clocks from the SCLK1 output is not
stopped until the specified number of bits are transmitted and re-
ceived.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
When the external synchronous clock is selected, input an “H”
level signal into the SBUSY1 input and an “L” level signal into the
SBUSY1 input in the initial status in which transfer is stopped. At
this time, the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 be-
come valid, enabling a transmit/receive operation, while an “L”
level signal is input into the SBUSY1 input and an “H” level signal is
input into the SBUSY1 input.
When changing the input values in the SBUSY1 input and the
SBUSY1 input at these operations, change them when the SCLK1
input is in a high state.
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, en-
abling serial transfer by inputting a transfer clock to SCLK1, while
an “L” level signal is input into the SBUSY1 input and an “H” level
signal is input into the SBUSY1 input.
Fig. 26 SSTB1 output operation
SSTB1
SCLK1
SOUT1
Serial transfer
status flag
SBUSY1
SCLK1
SOUT1
SBUSY1
SCLK1
SOUT1
Invalid
(Output high-impedance)
3. SBUSY1 output signal
The SBUSY1 output is a signal which requests a stop of transmis-
sion/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external syn-
chronous clock, whether the SBUSY1 output is to be active at
transfer of each 1-byte data or during transfer of all data can be
selected by the SBUSY1 output • SSTB1 output function selection bit
(b4).
In the initial status, the status in which the serial I/O initialization
bit (b4) is reset to “0”, the SBUSY1 output goes to “H” and the
SBUSY1 output goes to “L”.


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