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HM62W16258B Datasheet(PDF) 15 Page - Renesas Technology Corp

Part No. HM62W16258B
Description  4 M SRAM (256-kword ´ 16-bit)
Download  18 Pages
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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HM62W16258B Datasheet(HTML) 15 Page - Renesas Technology Corp

 
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HM62W16258B Series
13
Low V
CC Data Retention Characteristics (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ*
4
Max
Unit
Test conditions
*3
V
CC for data retention
V
DR
2.0
V
Vin
≥ 0V
(1)
CS
≥ V
CC – 0.2 V or
(2)
LB = UB
≥ V
CC – 0.2 V
CS
≤ 0.2 V
Data retention current
I
CCDR
*1
0.8
20
µAV
CC = 3.0 V, Vin ≥ 0V
(1)
CS
≥ V
CC – 0.2 V or
(2)
LB = UB
≥ V
CC – 0.2 V
CS
≤ 0.2 V
I
CCDR
*2
0.8
10
µA
Chip deselect to data
retention time
t
CDR
0
ns
See retention waveform
Operation recovery time
t
R
t
RC
*5
——
ns
Notes: 1. This characteristic is guaranteed only for L-version, 10
µA max. at Ta = 0 to +40°C.
2. This characteristic is guaranteed only for L-SL version, 5
µA max. at Ta = 0 to +40°C.
3.
CS controls address buffer, WE buffer, OE buffer, LB, UB buffer and Din buffer. If CS controls data
retention mode, Vin levels (address,
WE, OE, LB, UB, I/O) can be in the high impedance state. If
LB, UB controls data retention mode, LB, UB must be LB = UB
≥ V
CC – 0.2 V, CS must be CS ≤ 0.2
V. The other input levels (address,
WE, OE, I/O) can be in the high impedance state.
4. Typical values are at V
CC = 3.0 V, Ta = +25˚C and not guaranteed.
5. t
RC = read cycle time.


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