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HM62V16256C Datasheet(PDF) 17 Page - Renesas Technology Corp

Part No. HM62V16256C
Description  4 M SRAM (256-kword ´ 16-bit)
Download  20 Pages
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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HM62V16256C Datasheet(HTML) 17 Page - Renesas Technology Corp

 
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HM62V16256C Series
15
Low V
CC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter
Symbol
Min
Typ*
4
Max
Unit
Test conditions*
3
V
CC for data retention
V
DR
2.0
3.6
V
Vin
≥ 0V
(1) 0 V
≤ CS2 ≤ 0.2 V or
(2) CS2
≥ V
CC – 0.2 V
CS1
≥ V
CC – 0.2 V or
(3)
LB = UB
≥ V
CC – 0.2 V,
CS2
≥ V
CC – 0.2 V,
CS1
≤ 0.2 V
Data retention current
I
CCDR*
1
0.5
20
µAV
CC = 3.0 V, Vin ≥ 0V
(1) 0 V
≤ CS2 ≤ 0.2 V or
(2) CS2
≥ V
CC – 0.2 V,
CS1
≥ V
CC – 0.2 V or
(3)
LB = UB
≥ V
CC – 0.2 V,
CS2
≥ V
CC – 0.2 V,
CS1
≤ 0.2 V
I
CCDR*
2
0.5
10
µA
Chip deselect to data
retention time
t
CDR
0
ns
See retention waveform
Operation recovery time
t
R
t
RC*
5
——
ns
Notes: 1. This characteristic is guaranteed only for L-version, 10
µA max. at Ta = –20 to +40°C.
2. This characteristic is guaranteed only for L-SL version, 3
µA max. at Ta = –20 to +40°C.
3. CS2 controls address buffer,
WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If
CS2 controls data retention mode, Vin levels (address,
WE, OE, CS1, LB, UB, I/O) can be in the
high impedance state. If
CS1 controls data retention mode, CS2 must be CS2
≥ V
CC – 0.2 V or 0 V
≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high
impedance state.
4. Typical values are at V
CC = 3.0 V, Ta = +25˚C and not guaranteed.
5. t
RC = read cycle time.


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