HM62V16256C Series

10

Write Cycle

HM62V16256C

-5

Parameter

Symbol

Min

Max

Unit

Notes

Write cycle time

t

WC

55

—

ns

Address valid to end of write

t

AW

50

—

ns

Chip selection to end of write

t

CW

50

—

ns

5

Write pulse width

t

WP

40

—

ns

4

LB, UB valid to end of write

t

BW

50

—

ns

Address setup time

t

AS

0

—

ns

6

Write recovery time

t

WR

0

—

ns

7

Data to write time overlap

t

DW

25

—

ns

Data hold from write time

t

DH

0—

ns

Output active from end of write

t

OW

5

—

ns

2

Output disable to output in High-Z

t

OHZ

0

20

ns

1, 2

Write to output in high-Z

t

WHZ

0

20

ns

1, 2

Notes: 1. t

conditions and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. At any given temperature and voltage condition, t

and from device to device.

4. A write occures during the overlap of a low

CS1, a high CS2, a low WE and a low LB or a low UB.

A write begins at the latest transition among

CS1 going low, CS2 going high, WE going low and LB

going low or

UB going low. A write ends at the earliest transition among CS1 going high, CS2

going low,

WE going high and LB going high or UB going high. t

of write to the end of write.

5. t

6. t

7. t

cycle.