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HD151TS201ATEL Datasheet(PDF) 9 Page - Renesas Technology Corp |
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HD151TS201ATEL Datasheet(HTML) 9 Page - Renesas Technology Corp |
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9 / 29 page  HD151TS201AT Rev.1.00, Oct.21.2003, page 9 of 28 I 2C Controlled Register Bit Map (cont.) Byte2 PCI clock enable Register Bit Description Contents Default 7 (Reserved) 0 6 PCI6 Enable register 1 5 PCI5 Enable register 1 4 PCI4 Enable register 1 3 PCI3 Enable register 1 2 PCI2 Enable register 1 1 PCI1 Enable register 1 0 PCI0 Enable register “1” = Enabled “0” = Disabled (Each PCI clock stops “Low”) 1 Byte3 PCIF & USB, DOT enable Register Bit Description Contents Default 7 DOT output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 6 USB output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 5 Control of PCIF2 with PCISTOP# 0 4 Control of PCIF1 with PCISTOP# 0 3 Control of PCIF0 with PCISTOP# “1” = Not Free running. When this bit is “1”, PCIF outputs are stopped by PCISTOP# pin. “0” = Free running. 0 2 PCIF2 output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 1 PCIF1 output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 0 PCIF0 output enable 1 = Enable, 0 = Disable (DC Low fixed) 1 Byte4 66OUT, 3V66 Enable Register Bit Description Contents Default 7 Reserved 0 6 Reserved 0 5 3V66_0 Enable 1 = Enable, 0 = Disable (DC Low fixed) 1 4 3V66_1/VCH Enable 1 = Enable, 0 = Disable (DC Low fixed) 1 3 3V66_5 Enable 1 = Enable, 0 = Disable (DC Low fixed) 1 2 66OUT2/3V66_4 Enable 1 = Enable, 0 = Disable (DC Low fixed) 1 1 66OUT1/3V66_3 Enable 1 = Enable, 0 = Disable (DC Low fixed) 1 0 66OUT0/3V66_2 Enable 1 = Enable, 0 = Disable (DC Low fixed) 1 |
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