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M66312P Datasheet(PDF) 3 Page - Renesas Technology Corp |
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M66312P Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 9 page M66312P/FP REJ03F0178-0201 Rev.2.01 Mar 31, 2008 Page 3 of 8 Functional Description As M66312 uses silicon gate CMOS process, it realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shiftregister consists of two flip-flops having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when “L” changes to “H”. Serial data input A is the data input of the first-step shiftregister and the signal of A shifts shiting registers one by one when a pulse is impressed to CKS. When A is “H”, the signal of “H” shifts. When A is “L”, the signal of “L” shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the output from QA through QH are 3-state outputs. To extend the number of bits, serial data output SQH is used to output the 8-bit of the shift register. By connecting CKS and CKL, the shift register state delayed by 1 clock cycle is output at QA through QH. When reset input R is low, shift register and SQ H will be reset. To reset QA through QH to low-level, CKL must be changed from low-level to high-level after the shift register is reset by R. When output-enable input OE is high, Q A through QH will become high impedance state, but SQH is not changed. Even if OE is changed, shift operation is not affected. Function Table (Note) Operation Mode Reset Shift latch operation 3 state Input Parallel Data Output R L X H H H H X CK S X X ↑ X ↑ X X CK L X ↑ X ↑ X ↑ X A X X H X L X X OE L L L L L L H Q A Q A 0 L Q A 0 H Q A 0 L Z Q B Q B 0 L Q B 0 q A 0 Q B 0 q A 0 Z Q C Q C 0 L Q C 0 q B 0 Q C 0 q B 0 Z Q D Q D 0 L Q D 0 q C 0 Q D 0 q C 0 Z Q E Q E 0 L Q E 0 q D 0 Q E 0 q D 0 Z Q F Q F 0 L Q F 0 q E 0 Q F 0 q E 0 Z Q G Q G 0 L Q G 0 q F 0 Q G 0 q F 0 Z Q H Q H 0 L Q H 0 q G 0 Q H 0 q G 0 Z Shift t1 Latch t2 Shift t1 Latch t2 Shift t1 Latch t2 Serial Data Output SQ H L L q G 0 q G 0 q G 0 q G 0 q H Note ↑: Change from low-level to high-level Q 0: Output state Q before CK L changed X: Irrelevant q 0: Contents of shift register before CK S changed q: Contents of shift register t1, t2: t2 is set after t1 is set Z: High impedance |
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