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HD74LS95BFPEL Datasheet(PDF) 1 Page - Renesas Technology Corp |
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HD74LS95BFPEL Datasheet(HTML) 1 Page - Renesas Technology Corp |
1 / 7 page Rev.4.00, May 10, 2006, page 1 of 6 HD74LS95B 4-bit Parallel Access Shift Register REJ03D0424-0400 Rev.4.00 May 10, 2006 The 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register has three mode operation: • Parallel (broadside) load • Shift right (the direction Q A toward QD) • Shift left (the direction Q D toward QA) Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock-1 when the mode control is low; shift left is accomplished on the high-to-low transition of clock-2 when the mode control is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (QD to input C, etc.) and serial data is entered at input D. The clock input may be applied commonly to clock-1 and clock-2 if both modes can be clocked from the same source. Changes at the mode control inputs are low; however, conditions described in the last three lines of the function table will also ensure that register contents are protected. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS95BFPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP EL (2,000 pcs/reel) Pin Arrangement (Top view) GND 1 2 3 4 5 6 7 14 8 9 10 11 12 13 Serial Input Serial Input A A B B C C D D Mode Control Mode VCC QA QA QB QB QC QC Clock1 R-Shift CK1 QD QD Clock2 L-Shift (Load) CK2 Outputs Inputs |
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