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R8A66597FP Datasheet(PDF) 49 Page - Renesas Technology Corp |
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R8A66597FP Datasheet(HTML) 49 Page - Renesas Technology Corp |
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49 / 185 page  R8A66597FP/DFP/BG Rev 1.01 Oc t 17, 2008 page 49 of 183 ♦ Interrupt enabled register 2 [INTENB2] <Address: 34H> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OVRCRE BCHGE DTCHE ATTCHE EOFERRE 0 0 ? 0 0 ? ? ? ? 0 ? ? ? ? ? ? - - ? - - ? ? ? ? - ? ? ? ? ? ? Bit Name Function Software Hardware Remarks 15 OVRCRE Port1 OVRCR interrupt enabled Specify INT_N assert disabled/enabled while detecting Port1 OVRCR interrupt. 0: Interrupt output disabled 1: Interrupt output enabled R/W R H (Write to "0" when P)" 14 BCHGE Port1 USB bus change interrupt enabled Specify INT_N assert disabled/enabled while detecting Port1 BCHG interrupt. 0: Interrupt output disabled 1: Interrupt output enabled R/W R H (Write to "0" when P)" 13 Unassigned. Fix to "0". 12 DTCHE Port1 detach detect interrupt enabled Specify INT_N assert disabled/enabled while detecting Port1 DTCH interrupt (enabled only if HOST). 0: Interrupt output disabled 1: Interrupt output enabled R/W R H (Write to "0" when P)" 11 ATTCHE Port1 attach detect interrupt enabled Specify INT_N assert disabled/enabled while detecting Port1 ATTCH interrupt. 0: Interrupt output disabled 1: Interrupt output enabled R/W R H (Write to "0" when P)" 10-7 Unassigned. Fix to "0". 6 EOFERRE Port1 EOF error detect interrupt enabled Specify INT_N assert disabled/enabled while detecting Port1 EOFERR interrupt. 0: Interrupt output disabled 1: Interrupt output enabled R/W R H (Write to "0" when P)" 5-0 Unassigned. Fix to "0". Remarks * The interrupt enabled by the INTENB2 register can be written to only when the Host Controller function is selected. Do not enable it when the Peripheral Controller function is selected. 2.9.1 Interrupt enabled registers 0, 1, 2 (INTENB0, INTENB1, INTENB2) When the controller detects the interrupt corresponding to the bit for which the software has written "1" to the register, the controller asserts an interrupt from the INT_N pin. The controller sets "1" to this status bit corresponding to the INTSTS0, INTSTS1 and INTSTS2 registers when the detection conditions of each interrupt factor are satisfied, irrespective of the setup value of the register (interrupt notification disabled/enabled). When the status bit of the INTSTS0, INTSTS1 and INTSTS2 registers corresponding to each interrupt factor are set to "1", if the software modifies the interrupt enabled bit corresponding to the register from "0" to "1", the controller asserts the interrupt from the INT_N pin. |
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