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R8A66171SP Datasheet(PDF) 10 Page - Renesas Technology Corp |
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R8A66171SP Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 23 page R8A66171DD/SP REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 10 of 22 COMMAND-INSTRUCTION FORMAT The commands are decoded by D7 and D6. Note 1 : Priority is given to parity enable, if parity enable and CRC enable are both "1" (D3, D2=1). Note 2 : TxD output wave is Stop bit (D5) setup value +1 (always). D7 0 D6 0 D5 D4 D3 D2 D1 D0 ST EP PEN CRCEN BAUD PS Command1 1 : 1/32 division 0 : 1/2 division 1 : 2 bits 0 : 1 bit 1 : Even parity 0 : Odd parity 1 : Enable 0 : Disable 1 : To command2 (Baud rate setting) Prescaler Baud rate setting CRC enable Parity enable Parity check Stop bit Note2 1 : Enable 0 : Disable Command2 (Baud rate setting. The second byte when D1 bit of the command1 is set to "1".) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 ~ ~ ~ ~ ~ ~ ~ ~ ~ 1 1 1 1 1 1 1 1 255 n Command3 (Block length setting) 0 1 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 ~ ~ ~ ~ ~ ~ ~ 1 1 1 1 1 1 63 m D7 D6 |
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