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38K0 Datasheet(PDF) 43 Page - Renesas Technology Corp |
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38K0 Datasheet(HTML) 43 Page - Renesas Technology Corp |
43 / 133 page 38K0 Group Rev.3.00 Oct 05, 2006 page 43 of 129 REJ03B0192-0300 (3) Endpoint 02 Fig. 55 Structure of EP02 set register Fig. 56 Structure of EP02 control register 1 b7 b0 Double buffer beginning address set bit Buffer mode select bit Sequence toggle bit clear bit Interrupt toggle mode select bit Transfer direction bit Transfer type bite BSIZ02 [1:0] DBLB02 SQCL02 ITMD02 DIR02 TYP02 [1:0] – – – – – – 0 0 0 0 0 0 EP02 set register (EP02CFG) [address 001916] Bit name Bit symbol At reset Function H/W S/W In double buffer mode set the beginning address of buffer 1 area, using a relative value for the beginning address of buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : Single buffer mode 1 : Double buffer mode 0 : Toggle bit clear disabled 1 : Writing “1” clears the toggle bit and DATA0 is used as the next data PID. “0” is always read when reading. 0 : Normal mode 1 : Continuous toggle mode (valid at Interrupt IN transfer) 0 : OUT (Data is received from the host.) 1 : IN (Data is transmitted to the host.) b7b6 0 0 : Transfer disabled 0 1 : Bulk transfer 1 0 : Interrupt transfer 1 1 : Isochronous transfer O O O O O O O O O O O O –: State remaining W R b7 b0 Response PID bit Not used PID02 [1: 0] b7:b2 – – 0 – EP02 control register 1 (EP02CON1) [address 001A16] Bit name Bit symbol At reset Function H/W S/W b1 b0 0 0 : NAK 0 1 : Automatic response (ACK, NAK, DATA0, DATA1) 1 X : STALL At occurrence of over-max. packet size : B1 is set to “1” by the hardware. Write “0” when writing. “0” is read when reading. O O O O –: State remaining 00 0 0 00 W R |
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