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38D5 Datasheet(PDF) 93 Page - Renesas Technology Corp |
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38D5 Datasheet(HTML) 93 Page - Renesas Technology Corp |
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93 / 142 page  Rev.3.04 May 20, 2008 Page 93 of 134 REJ03B0158-0304 38D5 Group NOTES ON USE Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Initialize these flags at beginning of the program. Interrupt The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations • To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. • In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers The division ratio is 1/(n+1) when the value n (0 to 255) is written to the timer latch. Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Direction Registers The values of the port direction registers cannot be read. This means, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB, and read-modify- write instructions to direction registers, including calculations such as ROR. To set the direction registers, use instructions such as LDM or STA. Serial Interface In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O continues to output the final bit from the TXD pin after transmission is completed. A/D Converter The comparator is constructed linked to a capacitor. The conversion accuracy may be low because the charge is lost if the conversion speed is not enough. Accordingly, set f(XIN) to at least 500kHz during A/D conversion in the XIN mode. Also, do not execute the STP or WIT instruction during an A/D conversion. In the low-speed mode, since the A/D conversion is executed by the on-chip oscillator, the minimum value of f(XIN) frequency is not limited. LCD Drive Control Circuit Execution of the STP instruction sets the LCD enable bit (bit 4 of the LCD mode register) to “0” and the LCD panel turns off. To make the LCD panel turn on after returning from the stop mode, set the LCD enable bit to “1”. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (Vss pin), and between power source pin (VCC pin) and analog power source pin (AVCC). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.1 µF is recommended. LCD drive power supply Power supply capacitor may be insufficient with the division resistance for LCD power supply, and the characteristic of the LCD panel. In this case, there is the method of connecting the bypass capacitor about 0.1 −0.33µF to VL1 −VL3 pins. The example of a strengthening measure of the LCD drive power supply is shown below. Fig. 86 Strengthening measure example of LCD drive power supply • Connect by the shortest possible wiring. • Connect the bypass capacitor to the VL1 −VL3 pins as short as possible. (Referential value:0.1 −0.33 µF) VL3 VL2 VL1 |
Similar Part No. - 38D5_08 |
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Similar Description - 38D5_08 |
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