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3803L Datasheet(PDF) 50 Page - Renesas Technology Corp |
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3803L Datasheet(HTML) 50 Page - Renesas Technology Corp |
50 / 119 page Rev.1.01 Jan 25, 2008 Page 50 of 117 REJ03B0212-0101 3803 Group (Spec.L) Fig 43. Timing of serial I/O2 D7 D0 D1 D2 D3 D4 D5 D6 Transfer clock (1) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 register write signal (2) Serial I/O2 interrupt request bit set Notes1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or (f(XCIN) in low-speed mode, can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. |
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