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R1LV0414C-I Datasheet(PDF) 10 Page - Renesas Technology Corp

Part No. R1LV0414C-I
Description  Wide Temperature Range Version 4M SRAM (256-kword × 16-bit)
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Maker  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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R1LV0414C-I Datasheet(HTML) 10 Page - Renesas Technology Corp

 
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R1LV0414C-I Series
Rev.2.01, Nov.24.2005, page 10 of 11
Low VCC Data Retention Characteristics
(Ta =
−40 to +85°C)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions*
3
VCC for data retention
VDR
2
V
Vin
≥ 0V
(1) CS#
≥ VCC − 0.2 V or
(2) LB# = UB#
≥ VCC − 0.2 V,
CS#
≤ 0.2 V
to +85
°C
ICCDR
10
µA
to +70
°C
ICCDR
8
µA
to +40
°C
ICCDR
0.7*
2
3
µA
−5SI
to +25
°C
ICCDR
0.5*
1
3
µA
to +85
°C
ICCDR
20
µA
to +70
°C
ICCDR
16
µA
to +40
°C
ICCDR
0.7*
2
10
µA
Data
retention
current
−7LI
to +25
°C
ICCDR
0.5*
1
10
µA
VCC = 3.0 V, Vin
≥ 0V
(1) CS#
≥ VCC − 0.2 V or
(2) LB# = UB#
≥ VCC − 0.2 V,
CS#
≤ 0.2 V
Chip deselect to data retention time
tCDR
0
ns
See retention waveform
Operation recovery time
tR
tRC*
4
ns
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25
°C and specified loading, and not guaranteed.
2. Typical values are at VCC = 3.0 V, Ta = +40
°C and specified loading, and not guaranteed.
3. CS# controls address buffer, WE# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS# controls data
retention mode, Vin levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state. If LB#,
UB# controls data retention mode, LB#, UB# must be LB# = UB#
≥ VCC − 0.2 V, CS# must be CS# ≤ 0.2 V.
The other input levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. tRC = read cycle time.


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