HD151TS304RP

Rev.6.00 Apr 07, 2006 page 5 of 9

AC Electrical Characteristics / Clock Output & SSC Clock Output

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

Notes

—

| 250 |

| 300 |

SSCCLKOUT,

24 MHz

—

| 250 |

| 300 |

SSCCLKOUT,

48 MHz

SSCOFF

SEL1:0 = 10

Figure 1

—

| 250 |

| 300 |

SSCCLKOUT,

24 MHz

—

| 250 |

| 300 |

SSCCLKOUT,

48 MHz

SSC=

±0.25%

SEL1:0 = 11

Figure 1

—

| 250 |

| 300 |

SSCCLKOUT,

24 MHz

—

| 250 |

| 300 |

SSCCLKOUT,

48 MHz

SSC=

±1.5%

SEL1:0 = 01

Figure1

Cycle to cycle jitter

*1, 2

—

| 250 |

| 300 |

ps

CLKOUT,

24 MHz & 48MHz

Figure1

23.8

—

24.2

SSCCLKOUT,

XIN = 24 MHz

47.3

—

48.7

SSCCLKOUT,

XIN = 48 MHz

SSCOFF

SEL1:0 = 10

23.7

—

24.3

SSCCLKOUT,

XIN = 24 MHz

47.2

—

48.8

SSCCLKOUT,

XIN = 48 MHz

SSC=

±0.25%

SEL1:0 = 11

23.4

—

24.6

SSCCLKOUT,

XIN = 24 MHz

46.6

—

49.4

SSCCLKOUT,

XIN = 48 MHz

SSC=

±1.5%

SEL1:0 = 01

23.8

—

24.2

CLKOUT,

24 MHz

Output frequency

*1, 2

47.3

—

48.7

MHz

CLKOUT,

48 MHz

Slew rate

*1

1.0

—

—

V/ns

@48 MHz CLKOUT

0.4 V to 2.4 V

Clock duty cycle

*1

45

50

55

%

Output impedance

*1

—

30

—

Ω

Spread spectrum

modulation frequency

*1

—

33

—

KHz

@48 MHz

SSCCLKOUT

Input clock frequency

10

—

60

MHz

Stabilization time

*1,3

—

—

2

ms

Notes:

1. Parameters are target of design. Not 100% tested in production.

2. Cycle to cycle jitter and output frequency are included spread spectrum modulation.

3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up.

SSCCLKOUT

(or CLKOUT)

tcycle n

t

= (tcycle n) - (tcycle n+1)

CCS

tcycle n+1

Figure 1 Cycle to cycle jitter