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HD151BF854 Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # HD151BF854
Description  2.5 V PLL Clock Buffer for DDR Applicationjpeg
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD151BF854 Datasheet(HTML) 3 Page - Renesas Technology Corp

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HD151BF854
Rev.5.00 Apr 07, 2006 page 3 of 7
Logic Diagram
PLL
Test
Logic
CLKIN
AV
DD
10
8
20
FBIN
Y0
Y0
2
1
4
5
13
14
17
16
24
25
26
27
19
Y1
Y2
Y1
Y2
Y3
Y3
Y4
Y4
Y5
Y5
FBOUT
DDQ
Note: All inputs and outputs are associated with V
= 2.5 V.
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Conditions
Supply voltage
VDD
–0.5 to 3.6
V
VIC
–0.5 to 3.6
V
CLKIN
Input voltage
VI
–0.5 to VDD+0.5
V
Output voltage *
1
VO
–0.5 to VDD+0.5
V
Input clamp current
IIK
–50
mA
VI < 0
Output clamp current
IOK
–50
mA
VO < 0
Continuous output current
IO
±50
mA
VO = 0 to VDD
Maximum power dissipation
at Ta = 55°C (in still air)
0.7
W
Storage temperature
Tstg
–65 to +150
°C
Notes:
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.


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