HD151011

Rev.2.00, Jul.16.2004, page 3 of 13

Pin Description

Pin Name

Pin Description

Input pins

J0 to J7

Count data input for option

C/

T

Level change input for CLK,

CLK (CMOS level or TTL level)

CLK,

CLK

Clock inputs

CLK : Rise edge trigger

CLK : Fall edge trigger

SPE

Preset input for Jn data

PR

Preset input for D-type Flip Flop (Initialize “L” at Q output)

CLR

Clear input for D-type Flip Flop (Initialize “H” at Q output)

Output pins

CO

Output for BCD decimal counter

Q

Output for D-type Flip Flop

Absolute Maximum Ratings

Item

Symbol

Ratings

Unit

Supply voltage

V

CC

–0.5 to 7.0

V

Input/output voltage

V

–0.5 to V

V

V

I

±50

mA

Output current/pin

I

OUT

±25

mA

Power dissipation

P

T

757

mW

Storage temperature

Tstg

–65 to 150

°C

Input diode current

I

IK

±20

mA

Output diode current

I

OK

±20

mA

Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two

of which may be realized at the same time.

2. All voltage values except for differential input voltage are with respect to network ground terminal.

Recommended Operating Conditions

Item

Symbol

Min

Typ

Max

Unit

Supply voltage

V

CC

2—

6V

Input/output voltage

V

0—

V

CC

V

Operating temperature

Topr

–40

—

+85

°C

Input rise/fall time*

1

V

t

0

—

1000

ns

V

0

—

500

V

0

—

400

Note:

1. This item guarantees maximum limit when one input switches.

Logic Diagram

C/T

CLK

CLK

CLK

SPE

PR

CLR

PR

D

CK

Q

Q

CLR

Q

CO

CO

SPE

J0

J0

J1

J1

J2

J2

J3

J3

J4

J4

J5

J5

J6

J6

J7

J7