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CY7C603xx
Document #: 38-16018 Rev. *E
Page 10 of 31
Table 4. 32-Pin Part Pinout (QFN*)
Pin
No.
Type
Name
Description
Digital
Analog
1
IO
I, M
P0[1]
Analog Column Mux Input, Integrating Input.
2
IO
M
P2[7]
3
IO
M
P2[5]
4
IO
M
P2[3]
5
IO
M
P2[1]
6
IO
M
P3[3]
In CY7C60323 Part.
6
Power
SMP
Switch Mode Pump (SMP) Connection to required external components in CY7C60333
Part.
7
IO
M
P3[1]
In CY7C60323 Part.
7
Power
Vss
Ground Connection in CY7C60333 Part.
8
IO
M
P1[7]
I2C Serial Clock (SCL).
9
IO
M
P1[5]
I2C Serial Data (SDA).
10
IO
M
P1[3]
11
IO
M
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK.
12
Power
Vss
Ground Connection.
13
IO
M
P1[0]
I2C Serial Data (SDA), ISSP-SDATA.
14
IO
M
P1[2]
15
IO
M
P1[4]
Optional External Clock Input (EXTCLK).
16
IO
M
P1[6]
17
Input
XRES
Active HIGH External Reset with Internal Pull Down.
18
IO
M
P3[0]
19
IO
M
P3[2]
20
IO
M
P2[0]
21
IO
M
P2[2]
22
IO
M
P2[4]
23
IO
M
P2[6]
24
IO
I, M
P0[0]
Analog Column Mux Input.
25
IO
I, M
P0[2]
Analog Column Mux Input.
26
IO
I, M
P0[4]
Analog Column Mux Input.
27
IO
I, M
P0[6]
Analog Column Mux Input.
28
Power
Vdd
Supply Voltage.
29
IO
I, M
P0[7]
Analog Column Mux Input.
30
IO
I, M
P0[5]
Analog Column Mux Input.
31
IO
I, M
P0[3]
Analog Column Mux Input, Integrating Input.
32
Power
Vss
Ground Connection.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The QFN package has a center pad that must be connected to ground (Vss).
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