7 / 31 page  CY7C603xx Document #: 38-16018 Rev. *E Page 7 of 31 Pin Information The enCoRe III LV device is available in 28-pin SSOP and 32-pin QFN packages, which are listed and shown in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 28-Pin Part Pinout Figure 5. CY7C60323-PVXC 28-Pin Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] Vss M, I2C SCL, P1[7] M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M XRES P1[6], M P1[4], EXTCLK, M P1[2], M P1[0], I2C SDA, M SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Table 3. Pin Definitions - CY7C60323-PVXC 28-Pin Device Pin No. Type Name Description Digital Analog 1 IO I, M P0[7] Analog Column Mux Input. 2 IO I, M P0[5] Analog Column Mux Input and Column Output. 3 IO I, M P0[3] Analog Column Mux Input and Column Output, Integrating Input. 4 IO I, M P0[1] Analog Column Mux Input, Integrating Input. 5 IO M P2[7] 6 IO M P2[5] 7 IO I, M P2[3] Direct Switched Capacitor Block Input. 8 IO I, M P2[1] Direct Switched Capacitor Block Input. 9 Power Vss Ground Connection. 10 IO M P1[7] I2C Serial Clock (SCL). 11 IO M P1[5] I2C Serial Data (SDA). 12 IO M P1[3] 13 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK. 14 Power Vss Ground Connection. 15 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA. 16 IO M P1[2] 17 IO M P1[4] Optional External Clock Input (EXTCLK). 18 IO M P1[6] 19 Input XRES Active HIGH External Reset with Internal Pull Down. 20 IO I, M P2[0] Direct Switched Capacitor Block Input. 21 IO I, M P2[2] Direct Switched Capacitor Block Input. 22 IO M P2[4] 23 IO M P2[6] 24 IO I, M P0[0] Analog Column Mux Input. [+] Feedback |
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