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M24C32FCS5TG Datasheet(PDF) 27 Page - STMicroelectronics |
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M24C32FCS5TG Datasheet(HTML) 27 Page - STMicroelectronics |
27 / 39 page M24128, M24C64, M24C32 DC and AC parameters 27/39 Table 18. AC characteristics (M24xxx-F) Test conditions specified in Table 10 Symbol Alt. Parameter Min. Max. Unit fC fSCL Clock frequency 400 kHz tCHCL tHIGH Clock pulse width high 600 ns tCLCH tLOW Clock pulse width low 1300 ns tXH1XH2 (1) 1. Values recommended by the I²C-bus Fast-Mode specification. tR Input signal rise time 20 300 ns tXL1XL2 (1) tF Input signal fall time 20 300 ns tDL1DL2 tF SDA (out) fall time 20 100 ns tDXCX tSU:DAT Data in set up time 100 ns tCLDX tHD:DAT Data in hold time 0 ns tCLQX tDH Data out hold time 200 ns tCLQV (2)(3) 2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus × Cbus time constant is less than 500 ns (as specified in Figure 5). tAA Clock low to next data valid (access time) 200 900 ns tCHDX (4) 4. For a reStart condition, or following a Write cycle. tSU:STA Start condition set up time 600 ns tDLCL tHD:STA Start condition hold time 600 ns tCHDH tSU:STO Stop condition set up time 600 ns tDHDL tBUF Time between Stop condition and next Start condition 1300 ns tW Write time 10(5) 5. For temperature range 6: tW(max) = 5 ms. For temperature range 5: tW(max) = 10 ms. ms |
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