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MC145170P2 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc |
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MC145170P2 Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc |
18 / 32 page MC145170-2 Technical Data, Rev. 5 18 Freescale Semiconductor Design Considerations 4 Design Considerations 4.1 Crystal Oscillator Considerations The following options may be considered to provide a reference frequency to our CMOS frequency synthesizers. 4.1.1 Use of a Hybrid Crystal Oscillator Commercially available temperature-compensated crystal oscillators (TCXOs) or crystal-controlled data clock oscillators provide very stable reference frequencies. An oscillator capable of CMOS logic levels at the output may be direct or dc coupled to OSCin. If the oscillator does not have CMOS logic levels on the outputs, capacitive or ac coupling to OSCin may be used (see Figures 9 and 10). For additional information about TCXOs, visit www.freescale.com on the world wide web. 4.1.2 Use of the On-Chip Oscillator Circuitry The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in Figure 20. The crystal should be specified for a loading capacitance (CL) which does not exceed 20 pF when used at the highest operating frequencies listed in Table 6, Loop Specifications. Larger CL values are possible for lower frequencies. Assuming R1 = 0 Ω, the shunt load capacitance (CL) presented across the crystal can be estimated to be: where Cin = 5.0 pF (see Figure 21) Cout = 6.0 pF (see Figure 21) Ca = 1.0 pF (see Figure 21) C1 and C2 = external capacitors (see Figure 21) Cstray = the total equivalent external circuit stray capacitance appearing across the crystal terminals The oscillator can be “trimmed” on-frequency by making a portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSCin and OSCout pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. Circuit stray capacitance can also be handled by adding the appropriate stray value to the values for Cin and Cout. For this approach, the term Cstray becomes 0 in the above expression for CL. A good design practice is to pick a small value for C1, such as 5 to 10 pF. Next, C2 is calculated. C1 < C2 results in a more robust circuit for start-up and is more tolerant of crystal parameter variations. CL CinCout Cin Cout + ----------------------------Ca Cstray C1 C2 × C1 C2 + --------------------- ++ + = |
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