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M24C16RDS3TP Datasheet(PDF) 12 Page - STMicroelectronics

Part # M24C16RDS3TP
Description  16 Kbit, 8 Kbit, 4 Kbit, 2 Kbit and 1 Kbit serial I짼C bus EEPROM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24C16RDS3TP Datasheet(HTML) 12 Page - STMicroelectronics

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Device operation
M24C16, M24C08, M24C04, M24C02, M24C01
12/34
3.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 3 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the
device select code is received, the device only responds if the Chip Enable Address is the
same as the value on the Chip Enable (E0, E1, E2) inputs. However, those devices with
larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0
is not available for use on devices that need to use address line A8; E1 is not available for
devices that need to use address line A9, and E2 is not available for devices that need to
use address line A10 (see Figure 2 and Table 3 for details). Using the E0, E1 and E2 inputs,
up to eight M24C02 (or M24C01), four M24C04, two M24C08 or one M24C16 devices can
be connected to one I²C bus. In each case, and in the hybrid cases, this gives a total
memory capacity of 16 Kbits, 2 KBytes (except where M24C01 devices are used).
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 4.
Operating modes
Mode
RW bit
WC(1)
1.
X = VIH or VIL.
Bytes
Initial Sequence
Current Address Read
1
X
1
Start, Device Select, RW = 1
Random Address Read
0X
1
Start, Device Select, RW = 0, Address
1
X
reStart, Device Select, RW = 1
Sequential Read
1
X
≥ 1
Similar to Current or Random Address
Read
Byte Write
0
VIL
1
Start, Device Select, RW = 0
Page Write
0
VIL
≤16
Start, Device Select, RW = 0


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