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FSEZ1216 Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FSEZ1216 Datasheet(HTML) 11 Page - Fairchild Semiconductor |
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11 / 14 page  © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSEZ1216 • Rev. 1.0.0 11 Functional Description (Continued) Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds of the FSEZ1216 are fixed internally at 16V and 5V. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable the FSEZ1216. The hold-up capacitor continues to supply VDD until power can be delivered from the auxiliary winding of the main transformer. VDD must not drop below 5V during startup. The UVLO hysteresis window ensures the hold-up capacitor is adequate to supply VDD during startup. VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents damage due to over-voltage conditions. When the VDD voltage exceeds 28V due to abnormal conditions, PWM pulses are disabled until the VDD voltage drops below the UVLO, then starts again. Over-voltage conditions are usually caused by open feedback loops. Over-Temperature Protection (OTP) The FSEZ1216 has a built-in temperature sensing circuit to shut down PWM output once the junction temperature exceeds 140°C. While PWM output is shut down, the VDD voltage gradually drops to the UVLO voltage. Some of the internal circuits are shut down and VDD gradually starts increasing again. When VDD reaches 16V, all the internal circuits, including the temperature-sensing circuit, start operating normally. If the junction temperature is still higher than 140°C, the PWM controller shuts down immediately. This situation continues until the temperature drop below 110°C. Gate Output The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 15V Zener diode to protect the internal power MOSFET transistors against undesired over-voltage gate signals. Built-in Slope Compensation The sensed voltage across the current-sense resistor is used for current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillations due to peak-current-mode control. A synchronized, positively sloped ramp is built-in at each switching cycle. Noise Immunity Noise from the current sense or the control signal can cause significant pulse-width hopping, particularly in continuous-conduction mode. While slope compensation helps alleviate these problems, further precautions should still be taken. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FSEZ1216. |
Similar Part No. - FSEZ1216 |
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Similar Description - FSEZ1216 |
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